FIGS. 1a through 1e are cross-sectional views illustrating a known metallic interconnect fabrication method. Referring to FIG. 1a, a conductive material is filled into a via hole. In particular, an interlayer dielectric layer (hereinafter referred to as “IDL”) 1 is formed on a semiconductor substrate (not shown) having predetermined devices. A photoresist pattern for making a via hole is formed on the IDL 1 through a photoresist development process. Subsequently, a via hole is formed by etching the IDL 1. A preventive layer 2 is formed to protect the via hole from the diffusion of the metal. Preferably, the preventive layer comprises two layers, namely, a first layer and a second layer. In detail, the first layer comprising Ti is deposited as a liner layer by a sputtering process. Subsequently, the second layer comprising TiN is formed by a high pressure chemical vapor deposition (hereinafter referred to as “HPCVD”) process. A first conductive layer 3 to form a via plug is then deposited on the preventive layer of the resulting structure. Preferably, the first conductive layer to form the via plug is deposited by a chemical vapor deposition (hereinafter referred to as “CVD”) process and is made of tungsten.
Referring to FIG. 1b, the first conductive layer to form the via plug is removed by a planarization process such as a chemical mechanical polishing (hereinafter referred to as “CMP”) process using the IDL 1 as an etching stop layer.
Referring to FIG. 1c, a first preventive layer 4 is formed on the entire surface of the resulting structure. The first preventive layer 4 is preferably made of Ti/TiN by a sputtering process. Subsequently, a second conductive layer 5 to form a metallic interconnect is then deposited on the first preventive layer 4 by a sputtering process. A second conductive layer 5 to form the metallic interconnect is preferably made of Al. A second preventive layer 6 is then formed on the second conductive layer 5 by the sputtering process. The second preventive layer 6 is preferably made of an identical material used for the first preventive layer 4. The first and second preventive layers 4 and 6 prevent the penetration and the diffusion of the metal to form the metallic interconnect into other parts such as the IDL 1.
Referring to FIG. 1d, a photoresist pattern for making a desired metallic interconnect is formed on the second preventive layer 6. The metallic interconnect is then formed by etching the predetermined part of the first and second preventive layers 4 and 6 and the second conductive layer 5 using the IDL 1 as the etching stop layer.
According to the known method described above, the planarization process is performed using the IDL 1 as the etching stop layer, thereby causing several problems. One problem is that the protective layer made of Ti/TiN is also removed during the planarization process. Thus, another preventive layer (i.e., the first preventive layer) between the via hole and the metallic interconnect has to be formed, thereby increasing the contact resistance of the metallic interconnect.
FIG. 1e is an enlarged-view of a circle 8 in FIG. 1d. Referring to FIG. 1e, a later thermal treatment generates TiAl3 layers on both the upper and the bottom of the metallic interconnect. The TiAl3 layers result from the reaction of Ti in the first and second preventive layers and Al in the metallic interconnect. The TiAl3 layers lead to increase the resistance of the metallic interconnect, therefore increasing the RC-delay of the semiconductor device.